1. Field of the Invention
The invention relates to the field of computer memory management, and more particularly, the invention relates to the management of non-volatile solid state memory devices.
2. Description of the Related Art
As well-known in computer science, memory can be split into two categories: volatile and non-volatile. Volatile memory loses data when a computer system is turned off. In other words, it requires power to persist. Most types of random access memory (RAM) fall into this category. In contrast, non-volatile memory retains stored information even when a computer system is not powered-on. Usually, solid-state memory falls into the second category.
Non-volatile memory was originally called Read Only Memory (ROM); its loaded contents could be read but not erased or reprogrammed. The ability to erase or reprogram came along with the next generations of devices, namely Electrically Programmable ROM (EPROM), Electrically Erasable and Programmable ROM (EEPROM), and Flash EEPROM—the latter commonly referred to as Flash memory.
ROM memory is programmed at the time of manufacture; it stores permanent code and data (e.g. used to initialize and operate a computer system). EPROM can be electrically programmed one byte at a time but is not easily erasable. Yet, erasing all memory bits can be achieved by exposure to ultra-violet (UV) light. EPROM likely uses a single transistor for each data bit and allows for relatively high density memories. EEPROM is electrically erasable and programmable “in-system”, that is, one byte (or word) at a time. However, memory cells use more transistors and are larger than EPROM's. EEPROM has thus higher costs and lower density (e.g. less than 1 MB).
More recently, Flash EEPROM memory have been developed that can be electrically programmed a single byte at a time. Yet, erasing can only be achieved for at least one group of bytes at a time (also called a block or sector). All bytes in a block are electrically erased at the same time. The erase operation is much faster than in prior EPROM or EEPROM devices, whence the name of “Flash”. The Flash memory cell uses a single transistor to store one or more bits of information. It achieves the density of EPROM together with the versatility of electrical in-system erase and programmability of EEPROMs.
Furthermore, flash memory offers fast read access times (although generally not as fast as volatile DRAM used in PCs) and better kinetic shock resistance than hard disks. For these reasons, flash memory has become a dominant technology in solid state storage.
Flash memory stores information in an array of memory cells made from floating-gate transistors. In traditional single-level cell (SLC) devices, each cell stores only one bit of information. Some newer flash memory, known as multi-level cell (MLC) devices, can store more than one bit per cell by choosing between multiple levels of electrical charge to apply to the floating gates of its cells.
Apart from that it must be erased a “block” at a time, another limitation is that flash memory has a finite number of erase-write cycles. Most flash products withstand around 100,000 write/erase-cycles, before wear begins to deteriorate integrity of the storage. The guaranteed cycle count may apply only to block zero or to all blocks (depending on the device type).
This effect is partially offset in some chip firmware or file system drivers by counting the writes and dynamically remapping blocks in order to spread write operations between blocks. The technique is called wear-leveling. Typically, a memory unit subdivides into dies (also called IC dies or dice), and each die is composed of blocks. Blocks can be composed of pages, which decompose into cells.
Another approach is to perform write verification and remapping to spare blocks in case of a write failure (bad block management or BBM). These wearout management techniques extend the life of the flash memory for these applications where data loss is acceptable. For high reliability data storage, however, it is generally not advised to use flash memory that would have to go through a large number of programming cycles. Yet, this limitation is meaningless for ‘read-only’ applications such as thin clients and routers, which are only programmed at most a few times during their lifetime.
For clarity, the following definitions are used:                Bit: The basic unit of memory, “1” or “0”;        Byte: A group of 8 bits;        Cell: A physical semiconductor structure that stores one (or more) bit of data;        Write/Erase: The operation of altering an electronic state of (e.g. adding or removing electrons from) the storage medium of a memory cell in order to alter memory bits and so to write or erase encoded data; more generally to write/erase data on the device;        Read: The process of determining the state of the bit cell; more generally to read data stored on the device;        Endurance: Write/erase cycles a memory can endure before failure (typically 10 000 cycles);        Data Retention: Typically a time value pertaining to a memory cell's ability to retain data.        
Non-volatile memory cells have some important functional characteristics, which are used to evaluate the performance of the cell. These characteristics are divided into two main classes—endurance and retention. These are the two main challenges that solid-state-based non-volatile memories are faced with.
As mentioned above, endurance is defined as the maximum number of writes/erase cycles that can be performed on each cell before it wears out. When a non-volatile memory cell can no longer hold a charge in the floating gate, its retention capability is affected. Retention is thus a measure of the time that a non-volatile memory cell can retain the charge whether powered or not. Typically, data retention refers to the maximum time period during which the data can be read out, possibly with correctable errors. Endurance is typically specified assuming a ten-year data retention period.
On the one hand, wear-leveling is one of the most widely used techniques to cope with the problem of wear-out. The state-of-the-art of wear-leveling is based on a counter of write/erase cycles per block, aiming at balancing write/erase cycles among blocks so that no block receives excessive write/erase cycles. Wear-leveling is formally illustrated in FIG. 1. In FIG. 1, for a given non-volatile solid state memory device (as provided at step 100), write/erase cycles are monitored for each block of the memory (step 110′). Then, programming the memory (for example implementing wear-leveling, step 140) takes into account the write/erase cycles counted for each block.
On the other hand, if error-correcting codes (ECC) or forward error correction (FEC) codes are known. ECC or FEC denotes code in which each data signal conforms to specific rules of construction such that departures from that construction in the received signal can be automatically detected and corrected. If the number of errors is within the capability of the code being used, the decoder can fix the error by flipping the bits at those locations. ECCs or FECs are used for data retention purposes.